1. Field of the Invention
The present invention relates generally to semiconductor fabrication methods and, more particularly, to reliable wordline formation in semiconductor memories.
2. Description of Related Art
Semiconductor structures such as memories are frequently organized with multiple parallel conducting paths, known as wordlines, oriented in a direction orthogonal to that of underlying bit lines. The wordlines are formed of conducting material and are electrically isolated from one another. During manufacture, care must be taken to maintain electrical separation of wordlines in the face of ever-shrinking semiconductor device dimensions. This required electrical separation may be compromised by the presence of undesired conducting paths, known as stringers, formed from residual conducting material remaining after performing etch steps to create the wordlines.
Methods for assuring wordline separation in manufacturing processes applicable to larger geometries generally do not scale to smaller geometries. Maintaining critical dimensions when wordline pitch is less than 40 nm is particularly difficult using prior art methods.
A need thus exists in the prior art for a manufacturing method of reliable wordline formation applicable to small geometries.